Non-volatile semiconductor memory devices are widely used as memory storage in computers and other electronic appliances. In Single-Level Cell (SLC) memory devices, a charge-retaining gate in each memory cell of the device is designed to retain a charge, such that the gate can be in either a charged state or an erased state. Each memory cell may therefore store a single bit of data, one state representing a logical “1” (typically associated with the erased state) and the other state a logical “0” (typically associated with the charged state).
In Multi-Level Cell (MLC) memory, the gate in each memory cell may be set to four or more different voltage states, or ranges, thereby providing a data density of two or more data bits per cell. MLC memory is described, for example, in U.S. Pat. No. 5,043,940, to Harari, and in U.S. Pat. No. 5,172,338, to Mehrotra et al., which are incorporated herein by reference.
As the density of an MLC device increases, the ranges defining voltage states necessarily become narrower. Consequently, the tolerance to actual and apparent shifts in cell voltages is reduced. In flash memory, actual shifts in the charge stored in a cell can occur when reading, programming or erasing a neighboring cell, due to electrical coupling between cells, as well as due to leakage of charge through the oxide insulating the gate of the cell over long periods of storage time. Apparent shifts may also occur due to field coupling between cells, an effect described in U.S. Pat. No. 5,867,429, to Chen et al., and in U.S. Pat. No. 5,930,167, to Lee et al., which are incorporated herein by reference. U.S. Pat. No. 5,930,167 further describes selectively programming portions of a multi-state memory as cache memory, in only two states or with a reduced margin, in order to shorten the time necessary to initially program the data. This data is later read and re-programmed into the memory in more than two states, or with an increased margin.
In certain types of MLC memory, multiple bits are stored in a cell simultaneously, whereas in other types, bits may be stored incrementally. In the latter case, a first bit is written (or “programmed”) to the least significant bit (LSB) of the cell by increasing the charge of the cell by a first increment. A second bit may then be stored (to the most significant bit, or “MSB,” in a two-bit cell) by increasing the charge by a further increment. U.S. Patent Application Publication 2007/0133249, to Roohparvar, which is incorporated herein by reference, describes storing a single bit in a cell of an MLC device. The cells to be programmed are initially programmed with the desire data into either the least significant or most significant bit of the cell. A second programming operation programs reinforcing data that adjusts the threshold level of the cell to the appropriate level for the desired data.
U.S. Patent Application Publication 2006/0171210, to Nagashima et al., which is incorporated herein by reference, describes storing a flag with each block of cells of an MLC device. The flag indicates whether the cells of the block are to be programmed as SLC cells or as MLC cells.
U.S. Pat. No. 7,164,601, to Mitani et al., which is incorporated herein by reference, describes setting a bit of a storage address designation so as to determine whether data is stored by an SLC operation mode or by an MLC operation mode.